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1/19 www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. integrated current-mode buck-boost dc/dc controller automotive white led driver ic BD8112EFV-M description BD8112EFV-M is a white led driver with the capa bility of withstanding high input voltage (36v max). this driver has 2ch constant-current drivers integrated in 1-chip, which each channel can draw up to 150ma max, so that high brightness led driving can be realized. furthermore, a current-mode buck-boost dc/dc controller is also integrated to achieve stable operation against voltage input and also to remove the constraint of the number of leds in series connection. the brightness can be controlled by either pwm or vdac techniques. features 1) input voltage range 5.0 ? 30 v 2) integrated buck-boost cu rrent-mode dc/dc controller 3) two integrated led current driver channels (150 ma max. each channel) 4) pwm light modulation(minimum pulse width 25 s) 5) oscillation frequency accuracy 5% 6) built-in protection functions (uvlo, ovp, tsd, ocp, scp) 7) led abnormal status detection function (open/ short) 8) htssop-b24 package applications backlight for display audio, small type panels, etc. absolute maximum ratings (ta=25 ) parameter symbol rating unit power supply voltage v cc 36 v boot voltage v boot 41 v sw,cs,outh voltage v sw, v cs, v outh 36 v boot-sw voltage v boot-sw 7 v led output voltage v led1,2 36 v vreg, ovp, outl, fail1, fail2, leden, iset, vdac, pwm, ss, comp, rt, sync, en voltage v vreg, v ovp, v outl, v fail1, v fail2, v leden, v iset, v vdac, v pwm, v ss, v comp, v rt, v sync, v en -0.3 7 < v cc v power consumption pd 1.10 1 w operating temperatur e range topr -40 +105 storage temperature range tstg -55 +150 led maximum output current i led 150 2 3 ma junction temperature tjmax 150 *1 ic mounted on glass epoxy board measuring 70mm70mm 1.6mm, power dissipated at a rate of 8.8mw/ at temperatures above 25 . *2 dispersion figures for led maximum output current and v f are correlated. please refer to data on separate sheet. *3 amount of current per channel. operating conditions (ta=25 ) parameter symbol target value unit power supply voltage v cc 5.0 30 v oscillating frequency range f osc 250 600 khz external synchronization frequency range 4 5 f sync fosc 600 khz external synchronization pulse duty range f sduty 40 60 % *4 connect sync to gnd or open when not us ing external frequency synchronization. *5 do not switch between internal and external synchronization when an external synchronization signal is input to the device.
technical note 2/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. electrical characteristics (unless otherwise specified, vcc=12v ta=25 ) target value parameter symbol min typ max. unit conditions circuit current i cc - 7 14 ma en=hi, sync=hi, rt=open pwm=low, iset=open, c in =10 f standby current i st - 4 8 aen=low [vreg block (vreg)] reference voltage v reg 4.5 5 5.5 v i reg =-5ma, c reg =2.2 f [outh block] outh high-side on resistance r onhh 1.5 3.5 7.0 i on =-10ma outh low-side on resistance r onhl 1.0 2.5 5.0 i on =10ma over-current protection operating voltage v olimit vcc -0.66 vcc -0.6 vcc -0.54 v [outl block] outl high-side on resistance r onlh 2.0 4.0 8.0 i on =-10ma outl low ?side on resistance r onll 1.0 2.5 5.0 i on =10ma [sw block] sw low -side on resistance r on_sw 2.0 4.5 9.0 i on_sw =10ma [error amplifie block] led voltage v led 0.9 1.0 1.1 v comp sink current i compsink 15 25 35 av led =2v, vcomp=1v comp source current i compsource -35 -25 -15 av led =0v, vcomp=1v [oscillator block] oscillating frequency f osc 285 300 315 khz r t =100k [ovp block] over-voltage detection reference voltage v ovp 1.9 2.0 2.1 v v ovp =sweep up ovp hysteresis width v ohys 0.45 0.55 0.65 v v ovp =sweep down scp latch off delay time t scp 70 100 130 ms r t =100k [uvlo block ] uvlo voltage v uvlo 4.0 4.3 4.6 v vcc : sweep down uvlo hysteresis width v uhys 50 150 250 mv vcc : sweep up [led output block] led current relative dispersion width i led1 -3 - +3 % i led =50ma, i led1 =(i led /i led_avg -1) 100 led current absolute dispersion width i led2 -5 - +5 % i led =50ma, i led2 =(i led /50ma-1) 100 iset voltage v iset 1.96 2.0 2.04 v r iset =120k pwm minimum pulse width tmin 25 - - sf pwm =150hz, i led =50ma pwm maximum duty dmax - - 100 % f pwm =150hz, i led =50ma pwm frequency f pwm - - 20 khz duty=50%, i led =50ma vdac gain g vdac - 25 - ma/v v dac =0 2v, r iset =120k i led =vdac r iset gain open detection voltage v open 0.2 0.3 0.4 v v led = sweep down led short detection voltage v short 4.2 4.5 4.8 v v ovp = sweep up led short latch off delay time t short 70 100 130 ms rt=100k pwm latch off delay time t pwm 70 100 130 ms rt=100k [logic inputs (en, sync, pwm, leden)] input high voltage v inh 2.1 - 5.5 v input low voltage v inl gnd - 0.8 v input current 1 i in 20 35 50 a v in =5v (sync, pwm, leden) input current 2 i en 15 25 35 av en =5v (en) [fail output (open drain) ] fail low voltage v ol - 0.1 0.2 v i ol =0.1 a this product is not designed for use in radioactive environments.
technical note 3/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. electrical characteristic curves (reference data) (unless otherwise specified, ta=25 ) fig.1 vreg temperature characteristic fig.2 osc temperature characteristic fig.3 iled depend on vled fig.4 iled temperature characteristic fig.5 vdac gain fig.3 vdac gain fig.7 efficiency (led2 parallel 5 step) fig.8 efficiency (led2 parallel 7 step) fig.9 circuit current (switching off) fig.10 overcurrent detecting voltage temperature characteristic fig.11 en threshold voltage fig.12 pwm threshold voltage 4.5 4.7 4.9 5.1 5.3 5.5 -40 -15 10 35 60 85 t emp era tur e: ta [ ] output voltage:vreg [v] vcc=12v 200 240 280 320 360 400 -40 -15 10 35 60 85 temperature:ta [ ] switching frequency:fosc [khz] vcc=12v 45 47 49 51 53 55 0.5 1.5 2.5 3.5 4.5 led voltage:vled[v] outputcurrent :iled [ma] vcc= 12v 45 47 49 51 53 55 -40 -15 10 35 60 85 temp e rat ure: ta [ ] outputcur rent :iled [ma] vcc = 12v 0 10 20 30 40 50 0 0.5 1 1.5 2 vdac voltage:vdac[v] outputcurrent :iled [ma] 0 1 2 3 4 5 0 0.02 0.04 0.06 0.08 0.1 vdac voltage:vdac[v] outputcurrent :iled [ma] 25 40 55 70 85 100 50 100 150 200 250 total_io [ma] efficiency [%] vcc=30v 25 40 55 70 85 100 50 100 150 200 250 out put current [ma] efficiency [%] vcc=12v 0.0 2.0 4.0 6.0 0 6 12 18 2 4 3 0 36 supply voltage:vcc [v] output carrent:icc [ma] vcc=12v 0.54 0.56 0.58 0.60 0.62 0.64 0.66 -40 -15 10 35 60 85 temperature:ta [ ] output voltage:vcc-vcs [v] vcc=12v 0 2 4 6 8 10 012 345 en voltage:ven [v] output voltage:vreg [v] 0 2 4 6 8 10 012 345 pwm voltage:ven [v] outputcurrent :iled [ma]
technical note 4/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. dgnd rt comp err amp vin vreg vcc en rt ovp osc ss control logic uvlo tsd ss pwm led1 led2 current driver iset pgnd pwm c in r pc c pc c ss cs r iset fail1 vreg vdac gnd iset boot outh sw fail2 leden c out sync crt ccomp vreg ovp timer latch pwm ocp drv ctl slope ocp ovp open short detect timer latch short det open det outl block diagram and pin configuration pin layout pin function table BD8112EFV-M htssop-b24 fig.14 pin symbol function 1 comp error amplifier output 2 ss soft start time-setting capacitance input 3 vcc input power supply 4 en enable input 5 rt oscillation frequency-setting resistance input 6 sync external synchronization signal input 7 gnd small-signal gnd 8 pwm pwm light modulation input 9 fail1 failure signal output 10 fail2 led open/short detection signal output 11 leden led output enable pin 12 led1 led output 1 13 led2 led output 2 14 ovp over-voltage detection input 15 vdac dc variable light modulation input 16 iset led output current-setting resistance input 17 pgnd led output gnd 18 outl low-side external mosfet gate drive out put 19 dgnd low-side internal mosfet source out put 20 sw high-side external mosfet source pin 21 outh high-side external mosfet gate drive out pin 22 cs dc/dc current sense pin 23 boot high-side mosfet power supply pin 24 vreg internal reference voltage output 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 comp ss vcc en rt sync gnd pwm fail2 fail2 leden led1 vreg boot cs outh sw dgnd outl pgnd iset vdac ovp led2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 comp ss vcc en rt sync gnd pwm fail2 fail2 leden led1 vreg boot cs outh sw dgnd outl pgnd iset vdac ovp led2 fail1
technical note 5/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. 5v voltage reference (vreg) 5v (typ.) is generated from the vcc input voltage when the enable pin is set high. this voltage is used to power internal circuitry, as well as the voltage source for device pins that need to be fixed to a logical high. uvlo protection is integrated into the vr eg pin. the voltage regulation circuitry operates uninterrupted for output voltages higher than 4.45 v (typ.), but if output voltage drops to 4.3 v (typ.) or lower, uvlo engages and turns the ic off. connect a capacitor (creg = 2.2uf typ.) to the vreg termi nal for phase compensation. o peration may become unstable if creg is not connected. constant-current led drivers if less than four constant-current drivers are used, unused channels should be switched off via the leden pin configuration. the truth table for these pins is shown below. if a driver output is enabled but not used (i.e. left open), the ic?s open circuit-detection circuitry will operate. please keep the unused pins open. the leden terminals are pulled down internally in the ic, so if left open, the ic will recognize them as logic lo. however, they should be connected directly to vreg or fixed to a logic hi when in use. led led en 1 2 l on on h on off ? output current setting led current is computed vi a the following equation: i led = min [ vdac , viset (=2.0v)] / rset x gain [a] (min[vdac , 2.0v] = the smaller value of either vd ac or viset; gain = set by internal circuitry.) in applications where an external signal is used for output current control, a control voltage in the range of 0.0 to 2.0 v can be connected on the vdac pin to control according to the above equat ion. if an external control si gnal is not used, connect the vdac pin to vreg (do not leave the pin open as this may c ause the ic to malfunction). also, do not switch individual channels on or off via the leden pin while operating in pwm mode. the following diagram illustrates the relation between iled and gain. in pwm intensity control mode, the on/off state of each current driver is controlled directly by the input signal on the pwm pin; thus, the duty ratio of the input signal on the pwm pin equals the duty ratio of the led current. when not controlling intensity via pwm, fix the pwm terminal to a high voltage (100%). output light intensity is greatest at 100% input. pwm iled(50ma/div) pwm iled pwm=150hz duty=50% pwm=150hz duty=0.38% iled vs gain 2850 2900 2950 3000 3050 3100 3150 0 20 40 60 80 100 120 140 160 iled[ma] gain
technical note 6/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. buck-boost dc/dc controller ? number of leds in series connection output voltage of the dcdc converter is controlled such that t he forward voltage over each of the leds on the output is set to 1.0v (typ.). dcdc operation is perform ed only when the led output is operating. when two or more led outputs are operating simultaneously, the led voltage output is held at 1.0v (typ.) per led over th e column of leds with the highest vf value. the voltages of other led outputs are increased only in relation to the fluc tuation of voltage over this column. consideration should be given to the change in power dissipat ion due to variations in vf of the leds. please determine the allowable maximum vf variance of the total leds in series by using the description as shown below: vf variation allowable voltage 3.7v typ. = short detecting voltage 4.5v typ. led control voltage 1.0v typ. the number of leds that can be connected in series is limited due to the ope n-circuit protection circuit, which engages at 85% of the set ovp voltage. theref ore, the maximum output voltage of the under normal operation becomes 30.6 v (= 36 v x 0.85 , where ( 30.6 v ? 1.0 v) / vf > n [maximum number of leds in series]). ? over-voltage protection circuit (ovp) the output of the dcdc converter should be connected to the ov p pin via a voltage divider. in determining an appropriate trigger voltage of for ovp function, consider the total number of leds in series and the maximum variation in vf. also, bear in mind that over-current prot ection (ocp) is triggered at 0.85 x ovp trigger voltage. if t he ovp function engages, it will no t release unless the dcdc voltage drops to 72.5% of the ovp trigger voltage. for exam ple, if rovp1 (out put voltage side), rovp2 (gnd side), and dcdc voltage vout are conditions for ovp, then: vout ( rovp1 + rovp2 ) / rovp2 x 2.0 v. ovp will engage when vout R 32 v if rovp1 = 330 k ? and rovp2 = 22 k ? . ? buck-boost dc/dc converter oscillation frequency (fosc) the regulator?s internal triangular wave oscillation frequency can be set via a resistor connected to the rt pin (pin 5). this resistor determines the charge/discharge current to the internal capacitor, thereby changing the oscillating frequency. refer to the fo llowing theoretical formula when setting rt: fosc = x [khz] 30 x 10 6 (v/a/s) is a constant (5%) determined by the internal circuitry, and is a correction factor that varies in relation to rt: { rt: = 50k ? : 0.94, 60k ? : 0.985, 70k ? : 0.99, 80k ? : 0.994, 90k ? : 0.996, 100k ? : 1.0, 150k ? : 1.01, 200k ? : 1.02, 300k ? : 1.03, 400k ? : 1.04, 500k ? : 1.045 } a resistor in the range of 47k ? 523k ? is recommended. settings that deviate fr om the frequency range shown below may cause switching to stop, and proper operation cannot be guaranteed. fig.15 rt versus switching frequency ? external dc/dc converter oscillating frequency synchronization (fsync) do not switch from external to internal oscillation of the dc/ dc converter if an external synchronization signal is present on the sync pin. when the signal on the sync terminal is switched from high to low, a delay of about 30 s (typ.) occurs before the internal oscillation circuitry starts to operate (only the rising edge of the input clock signal on the sync termina l is recognized). moreover, if external input frequency is less t han the internal oscillation frequency, the internal oscillator wi ll engage after the above-mentioned 30 s (typ.) delay; thus, do not input a synchronization signal with a frequency less than the internal oscillation frequency. ? soft start function the soft-start (ss) limits the current and slows the rise-time of the output volt age during the start-up, and hence leads to prevention of the overshoot of the output voltage and the inrush current. 50k 150k 250k 350k 450k 550k 0 100 200 300 400 500 600 700 800 rt [k] ? [khz] 30 10 6 rt [ ] frequency
technical note 7/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. ? self-diagnostic functions the operating status of the built -in protection circuitry is propagated to fa il1 and fail2 pins (open- drain outputs). fail1 becomes low when uvlo, tsd, ovp, or scp protection is engaged, whereas fail2 becomes low when open or short led is detected. ? operation of the protection circuitry ? under-voltage lock out (uvlo) the uvlo shuts down all the circuits other than reg when vreg Q 4.3v (typ). ? thermal shut down (tsd) the tsd shuts down all the circuits other than reg when the tj reaches 175 (typ), and releases when the tj becomes below 150 (typ). ? over current protection (ocp) the ocp detects the current through the power-fet by monitoring the voltage of the high-side resistor, and activates when the cs voltage becomes less than vcc-0.6v (typ). when the ocp is activated, the external capacitor of the ss pin becomes discharged and the switching operation of the dcdc turns off. ? over voltage protection (ovp) the output voltage of the dcdc is detected with the ovp-pin voltage, and the protection activates when the ovp-pin voltage becomes greater than 2.0v (typ). when the ovp is activated, the external capacitor of the ss pin becomes dischar ged and the switchin g operation of the dcdc turns off. ? short circuit protection (scp) when the led-pin voltage becomes less than 0.3v (typ), the in ternal counter starts operati ng and latches off the circuit approximately after 100ms (when fosc = 300khz). if the le d-pin voltage becomes over 0.3v before 100ms, then the counter resets. when the led anode (i.e. dcdc output voltage) is shorted to ground, then the led current becomes off and the led-pin voltage becomes low. furthermore, the led current also becomes off when the led cathode is shorted to ground. hence in summary, the scp works with both cases of the led anode and the cathode being shorted. ? led open detection when the led-pin voltage 0.3v (typ) as well as ovp-pin voltage 1.7v (typ) simultaneously, the device detects as led open and latches off that particular channel. uvlo tsd ovp ocp s r q counter scp en=low uvlo/tsd fail1 open short s r q en=low uvlo/tsd fail2 mask
technical note 8/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. ? led short detection when the led-pin voltage 4.5v (typ) as well as ovp-pin voltage 1.6v (typ) simultaneously the internal counter starts operating, and approximately after 100ms (when fosc = 300khz) the only detected channel (as led short) latches off. with the pwm brightness control, t he detecting operation is processed only wh en pwm-pin = high. if the condition of the detection operation is released before 100ms (when fosc = 300khz), then the internal counter resets. the counter frequency is the dcdc switching frequency determined by the rt. the latch proceeds at the count of 32770. detecting condition protection [detect] [release] operation after detect uvlo vreg<4.3v vreg>4.45v all blocks (but except reg) shut down tsd tj>175 tj<150 all blocks (but except reg) shut down ovp vovp>2.0v vovp<1.45v ss discharged ocp vcs Q vcc-0.6v vcs>vcc-0.6v ss discharged scp vled<0.3v (100ms delay when fosc=300khz) en or uvlo counter starts and then latches off all blocks (but except reg) led open vled<0.3v & vovp>1.7v en or uvlo the only detected channel latches off led short vled>4.5v & vovp<1.6v (100ms delay when fosc=300khz) en or uvlo the only detected channel latches off (after the counter sets)
technical note 9/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. protection sequence case for led2 in open-mode when vled2 0.3v and vovp 1.7v simultaneously, then led2 becomes off and fail2 becomes low case for led1? in short-mode when vled1? 4.5v and vovp 1.6v simultaneously, then led1? becomes off after 100ms approx case for led2? in short to gnd -1 dcdc output voltage increases, and then ss dichages and fail1 becomes low -2 detects vled2?<0.3v and shuts down after 100ms approx 1 after vcc voltage reached to operating conditions, set vdac voltage, and turn on the en. after vreg R 4.6v, turn on sync and pwm inputs. 2 don?t care input sequence pwm and sync. 3 aprox 100ms of delay when fosc = 300khz 4 when fail1 pull-up to outside power supply. vcc en uvlo vdac sync pwm ss iled1 iled2 iled1' iled2' vled1 vled2 vled1' vled2' vovp fail1 fail2 4.45v 1.0 <0.3 >4.7 100ms 3 0.3v 100ms 3 2.0v 1.7v 1 2 2 1 4 vreg >4.5
technical note 10/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. procedure for external components selection follow the steps as shown below for selecting the external components 1. work out il_max from the operating conditions. 2. select the value of rsc such that iocp > il_max 3. select the value of l such that 0.05[v/s] < l vout *rcs < 0.3[v/ s] 4. select coil, schottky diodes, mosfet and rcs which meet with the ratings 5. select the output capacitor which meets with the ripple voltage requirements 6. select the input capacitor 7. work on with the compensation circuit 8. work on with the over-voltage protection (ovp) setting 9. work on with the soft-start setting 10. verify experimentally feedback the value of l
technical note 11/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. 1. computation of the input peak current and il_max calculation of the maximu m output voltage (vout_max) to calculate the vout_max, it is necessary to take into a ccount of the vf variation and the number of led connection in series. vout_max = (v f + v f ) n + 1.0v v f : vf variation n: number of led connection in series calculation of the output current iout iout = i led 1.05 m m number of led connection in parallel calculation of the input peak current i l_max i l_max = i l_avg + 1/2 i l i l_avg = (v in + vout) iout / (n v in ) i l = n: efficiency fosc: switching frequency ? the worst case scenario for vin is when it is at the mini mum, and thus the minimum value should be applied in the equation. ? the l value of 10f 47f is recommended. the current-mode type of dc/dc conversion is adopted for BD8112EFV-M, which is optimized with the use of the recommended l value in the design stage. this recommendation is based upon the efficiency as well as the stability. the l values outside this recommended range may cause irregular switching waveform and hence deteriorate stable operation. ? n (efficiency) is approximately 80% external application circuit 2. the setting of over-current protection choose rcs with the use of the equation vocp_min (=0.54v) / rcs > i l_max when investigating the margin, it is worth noting t hat the l value may vary by approximately 30%. 3. the selection of the l in order to achieve stable operation of the current-mode dc/dc converter, we recommend selecting the l value in the range indicated below: 0.05 [v/s] < < 0.3 [v/s] the smaller allows stability improvement but slows down the response time. 4. selection of coil l, diode d1 and d2, mosfet m1 and m2, and rcs current rating voltage rating heat loss coil l > i l_max D diode d1 > iocp > vin_max diode d2 > iocp > vout mosfet m1 > iocp > vin_max mosfet m2 > iocp > vout rcs D D > iocp 2 rcs allow some margin, such as the tolerance of the external components, when selecting. in order to achieve fast switching, choose the mosfets with the smaller gate-capacitance. v in l 1 fosc vout v in +vout vout rcs l v in rcs d1 l d2 m2 m1 co vout i l cs vout rcs l
technical note 12/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. 5. selection of the output capacitor select the output capacitor cout based on th e requirement of the ripple voltage vpp. vpp = + i l_min r esr choose cout that allows the vpp to settle within the requirem ent. allow some margin also, su ch as the tolerance of the external components. 6. selection of the input capacitor a capacitor at the input is also required as the peak curr ent flows between the input and the output in dc/dc conversion. we recommend an input capacitor greater than 10f with the esr smaller than 100m . the input capacitor outside of our recommendation may cause large ripple voltage at the input and hence lead to malfunction. 7. phase compensation guidelines in general, the negative feedback loop is stable when the following condition is met: ? overall gain of 1 (0db) with a phase lag of less than 150o (i.e., a phase margin of 30o or more) however, as the dc/dc converter constantly samples the switch ing frequency, the gain-bandwidth (gbw) product of the entire seri es should be set to 1/10 the switching frequency of the system. therefore, the overall stability characteristics of the applicati on are as follows: ? overall gain of 1 (0db) with a phase lag of less than 150o (i.e., a phase margin of 30o or more) ? gbw (frequency at gain 0db) of 1/10 the switching frequency thus, to improve response within the gbw product limits, the switching frequency must be increased. the key for achieving stability is to place fz near to the gbw. phase-lead fz = [hz] phase-lag fp1 = [hz] good stability would be obtained when the fz is set between 1khz 10khz. in buck-boost applications, right-hand-plane (rhp) zero exists. th is zero has no gain but a pole characteristic in terms of phase. as this zero would cause instability when it is in the c ontrol loop, so it is necessary to bring this zero before the gbw. frhp= [hz] i load : m aximum l oad c urrent it is important to keep in mind that these are very l oose guidelines, and adjustments may have to be made to ensure stability in the actual circuitry. it is also important to not e that stability characteristics can change greatly depending on factors such as substrate layout and load conditions. ther efore, when designing for mass-production, stability should be thoroughly investigated and confirm ed in the actual physical design. iout cout vout vout+v in 1 fosc 1 2 cpcrpc fb a comp v out rpc led cpc 1 2 rlcout 2 i load l vout+vin/(vout+vin)
technical note 13/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. 8. setting of the over-voltage protection we recommend setting the over-voltage protection vovp 1.2v to 1.5v greater than vout which is adjusted by the number of leds in series connection. less than 1.2v may cause unexpected detection of the led open and short during the pwm brightness control. fo r the vovp greater than 1.5v, the led short detection may become invalid. 9. setting of the soft-start the soft-start allows minimization of the coil current as we ll as the overshoot of the output voltage at the start-up. for the capacitance we recommend in the range of 0.001 0.1uf. for the capacitance less than 0.001uf may cause overshoot of the output voltage. for the capacitance greater than 0.1uf may c ause massive reverse current through the parasitic elements of the ic and damage the whole device. in case it is necessary to use the capacitanc e greater than 0.1uf, ensure to have a reverse current protection diode at the vcc or a bypass diode placed between the ss-pin and the vcc. soft-start time tss tss = cssx0.7v / 5ua [s] css: the capacitance at the ss-pin 10. verification of the operation by taking measurements the overall characteristic may change by load current, input voltage, output voltage, inductance, load capacitance, switching frequency, and the pcb layout. we strongly re commend verifying your design by taking the actual measurements. 2.0v/1.45v 1.7v/1.6v ovp vo rovp2 rovp1
technical note 14/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. power dissipation calculation power dissipation can be calculated as follows: pc(n) = icc*vcc + 2*ciss*vreg*fsw*vcc+[vled*n+ vf*(n-1)]*iled i cc maximum circuit current v cc supply power voltage c iss external fet capacitance v sw sw gate voltage f sw sw frequency v led led control voltage n led parallel numeral v f led v f fluctuation i led led output current sample calculation: pc(2) = 10ma 30v + 500pf 5v 300khz 30v + [1.0v 2 + vf 1] 100ma when vf = 3.0v, pc (2) = 0.82w fig.26 note 1: power dissipation calculated when mounted on 70mm x 70 mm x 1.6mm glass epoxy substrate (1-layer platform/copper thickne ss 18 m) note 2: power dissipation changes with the copper foil density of the board. this value represents only observed values, not g uaranteed values. ambient temperature ta[ ] 150 125 100 75 50 105 0 0.5 1.0 1.5 2.0 25 1.1w power dissipation pd [w] power dissipation
technical note 15/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. ? the coupling capacitors cvcc a nd creg should be mounted as close as possible to the ic?s pins. ? large currents may pass through dgnd and pgnd, so each should have its own low-impedance routing to the system ground. ? noise should be minimized as much as possible on pins vdac, iset,rt and comp. ? pwm, sync and led1,2 carry switching signals, so ensure during layout that surrounding traces are not affected by crosstalk. 1. comp 2. ss 3. vcc 4. en 5. rt 6. sync 7. gnd fin. fin 8. pwm 9. fail1 10. fail2 11. leden 12. led1 13. led2 24. vreg 23. boot 22. cs 21. outh 20. sw 19. dgnd 18. outl fin. fin 17. pgnd 16. iset 15. vdac 14. ovp vcc vcc cin1 cin2 cpc2 cpc1 rpc1 css en sw1 crt rrt sync cin3 pwm rfl1 rfl2 vreg fail1 fail2 vreg sw2 led1 led2 vdac rdac vreg ciset riset d1 l1 d g m2 s cout1 cout2 d2 rovp1 rovp2 cbt creg m1 s d g rcs5 vreg vout ccs rcs1 rcs2 rcs3
technical note 16/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. how to select parts of application serial no. component name component value product name manufacturer 1 cin1 10 f grm31cb31e106ka75b murata 2 cin2 3 cin3 4 cpc1 0.1 f 5 cpc2 murata 6 rpc1 510 ? 7 css 0.1 f grm188b31h104ka92 murata 8 rrt 100k ? mcr03 series rohm 9 crt 10 rfl1 100k ? mcr03 series rohm 11 rfl2 100k ? mcr03 series rohm 12 ccs 13 rcs1 620m ? mcr100jzhfsr620 rohm 14 rcs2 620m ? mcr100jzhfsr620 rohm 15 rcs3 16 rcs5 0 ? 17 creg 2.2 f grm188b31a225ke33 murata 18 cbt 0.1 f grm188b31h104ka92 murata 19 m1 rss070n05 rohm 20 m2 rss070n05 rohm 21 d1 rb050l-40 rohm 22 d2 rf201l2s rohm 23 l1 33 h cdrh105r330 sumida 24 cout1 10 f grm31cb31e106ka75b murata 25 cout2 10 f grm31cb31e106ka75b murata 26 rovp1 30k ? mcr03 series rohm 27 rovp2 360k ? mcr03 series rohm 28 riset 120k ? mcr03 series rohm 29 ciset 30 rdac 0 ? when performing open/short tests of the external components, the open condition of d1 or d2 may cause permanent damage to the driver and/or the external components. in or der to prevent this, we recommend having parallel connections for d1 and d2.
technical note 17/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. interfaces input/output equivalent circuits (terminal name follows pin number) 1. comp 2. ss 4. en 5. rt 6. sync, 8. pwm 9. fail1, 10. fail2 11. leden 12. led1, 13. led2 14. ovp 15. vdac 16. iset 18. outl 20. sw 21. outh 22. cs 23. boot 24. vreg all values typical. cs 5k vcc sw vcc comp 2k 2k vreg vreg 1k ss vcc vreg en 175k 135k 10k vcc rt vreg 167 10k 3.3v 150k sync pwm 1k fail1 fail2 2.5k 5k led1,2 500 vdac vcc vreg 500 iset vcc 12.5 vreg vreg 100k outl vreg boot 100k outh boot sw sw sw vreg boot sw vreg vcc vreg 205k 100k 10k 3.3v 150k leden 10k ovp 10k vcc
technical note 18/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. notes for use 1 absolute maximum ratings we are careful enough for quality control about this ic. so, there is no problem under normal operat ion, excluding that it exce eds the absolute maximum ratings. however, this ic might be destroyed when the absolute maximum ratings, such as impressed voltages or the operating temperature range(topr), is exceeded, and whether the destruction is short circuit mode or open circuit mode cannot b e specified. please take into consideration th e physical countermeasures for safety, such as fu sing, if a particular mode that exceeds the a bsolute maximum rating is assumed. 2 reverse polarity connection connecting the power line to the ic in reverse polarity (from that recommended) will damage the part. please utilize the direct ion protection device as a diode in the supply line. 3 power supply line due to return of regenerative current by reverse electromotive force, using electrolytic and ce ramic suppress filter capacitors (0.1 f) close to the ic power input terminals (vcc and gnd) are recommended. pl ease note the electrolytic capaci tor value decreases at lower temperatures and examine to dispens e physical measures for safety. and, for ics with more than one power supply, it is possible t hat rush current may flow instantaneously due to the internal pow ering sequence and delays. therefore, give special consideration to power coupling capacitanc e, width of power wiring, gnd wiring, an d routing of wiring. please make the power supply li nes (where large current flow) wide enough to reduce the resistance of the power supp ly patterns, because the resistance of power supply patte rn might influence t he usual operation. 4 gnd line the ground line is where the lowest potential and transient voltages are connected to the ic. 5 thermal design do not exceed the power dissipation (pd) of the package spec ification rating under actual operation, and pl ease desi gn enough temperature margins. 6 short circuit mode between te rminals and wrong mounting do not mount the ic in the wrong direction and be careful about the reverse-connection of the pow er connector. moreover, this i c might be destroyed when the dust short the terminal s between them or power supply, gnd. 7 radiation strong electromagnetic radiati on can cause operation failures. 8 aso(area of safety operation.) do not exceed the maximum aso and the absol ute maximum ratings of the output driver 9 tsd(thermal shut-down) the tsd is activated when the junc tion temperature (tj) reaches 175 (with 25 hysteresis), and the output te rminal is switched to hi-z. the tsd circuit aims to interc ept ic from high temperature. the guarantee and pr otection of ic are not purpose. therefore, plea se do not use this ic after tsd circuit operates, nor use it for assumpti on that operates the tsd circuit. 10 inspection by the set circuit board the stress might hang to ic by connecting the capacitor to the te rminal with low impedance. t hen, please discharge electricity in each and all process. moreover, in the inspection process, please turn off the power before mounting the ic, and turn on after mounting the ic. in addition, please take into consider ation the countermeasures for el ectrostatic damage, such as giving the earth in assembly pro cess, transportation or preservation. 11 ic terminal input this ic is a monolithic ic, and has p + isolation and p substrate for the element separation. therefore, a pa rasitic pn junction is firmed in this p-layer and n-layer of each element. for instance, the resist or or the transistor is connect ed to the terminal as shown in the figure below. when the gnd voltage potential is greater than the voltage potent ial at terminals a or b, th e pn junction operates as a parasitic diode. in addition, the parasitic npn trans istor is formed in said parasitic diode and the n layer of surrounding elements clos e to said parasitic diode. these parasitic elements are formed in the ic because of the voltage relation. the parasitic element operating causes the wrong operation and destruction. therefore, pl ease be careful so as not to operate the parasitic elements by impressing to inpu t terminals lower voltage than gnd(p substrate). please do not apply the volt age to the input terminal w hen the power-supply voltage is not impressed. moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the guarant eed voltage when the power-supply voltage is impressing. simplified structure of ic 12 earth wiring pattern use separate ground lines for control signals and high current power driver outputs. be cause these high current outputs that fl ows to the wire impedance changes the gnd voltage for c ontrol signal. therefore, each ground termi nal of ic must be connected at the one p oint on the set circuit board. as for g nd of external parts, it is similar to the above-mentioned.
technical note 19/19 BD8112EFV-M www.rohm.com 2009.09 - rev.b ? 2009 rohm co., ltd. all rights reserved. htssop-b24 (unit : mm) htssop-b24 0.65 1.0max 0.85 0.05 0.08 0.05 0.24 +0.05 - 0.04 0.08 m s 0.08 1.0 0.2 0.53 0.15 0.17 +0.05 - 0.03 4 + 6 ? 4 s 24 13 112 0.325 (3.4) (5.0) 7.8 0.1 7.6 0.2 5.6 0.1 (max 8.15 include burr) 1pin mark unit:mm )

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